Continuing improvements in the integration density of semiconductor circuit architectures have resulted in a substantial increase in the complexity of building blocks (both custom and non-application specific components) available to the (digital) signal processing system designer. Indeed, chip architectures may employ hundreds of thousands of logic gates to implement a prescribed signal processing function. Because the extremely large number of gates employed in a given architecture prevent it from being adequately tested by conventional vector-based test methodologies (which use only input and output pins of the chip), the incorporation of one or more test access, or `sense`, circuitry components (e.g. sense MOSFET switches) into each cell has been proposed, in order to allow an external testing system to gain access to critical nodes within the cell and thereby evaluate the functionality of each cell.
The fact that each cell is to contain such auxiliary test access circuitry means that, in addition to the normal interconnect highways provided for normal signal processing flow, the topography of the multi-cell architecture must include additional links to provide test access paths between each cell and the testing mechanism. Now, although it is possible to selectively form and interconnect runs of polysilicon to the control inputs of test access switching components (e.g. the gates of MOSFET sense transistors), because of the relatively long distances (thousands of microns of a typical VLSI architecture) of interconnect required, the resulting resistance and parasitic capacitance of the polysilicon layer becomes prohibitively high, which greatly increases access time. An additional problem is how to configure and place the test access circuitry within the standard cell, so as to keep the occupation area of each cell as small as possible.